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ibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cdu100 is
port(CLK:in std_logic;
Q:inout std_logic_vector(7 downto 0);
COUT:out std_logic);end cdu100;architecture three of cdu100 is signal cout1,cout2:std_logic_vector(3 downto 0);begin
Q
then if(cout2=9 and cout1=9)then cout2
else if(cout1=9)then cout2
else cout2
end if;
end if;end if;if(cout2=9 and cout1=9)then COUT
