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无线局域网接收器的高效自动增益控制算法和结构
Il-Gu Lee *, Sok-Kyu Lee 下一代无线局域网研究团队，电子和电信研究院，柯亭161栋，顾儒城区，大田305700，大韩民国
2006年2月23日收稿；2006年10月31日收到修订的稿件；2006年11月1日收录
2007年1月11日可在线使用
摘要
接收机的性能前端限制了所给定的通信链路的质量和范围。基于明确定义的系统参数和结构的设计可以使整个系统在性能、成本和市场化方面有巨大的差异。值得强调的是，我们需要一种改进的数字自动增益控制(AGC)，应用于多输入多输出、正交频分复用(mimoOFDM系统，该系统工作在 5 GHz频带。图1和2显示了下一代无线局域网的数据包结构，该结构在文献[1,2]中有详细描述。每个数据包包含一个检测头，预测信道和同步信道。报头可以被双方识别以用来通信链接。传统的OFDM报头由10个相同的短正交频分复用(OFDM)辅助符号（ti，i = 1，2……10；每个符号包含16个样品）和2个相同的长正交频分复用(OFDM)辅助符号（Ti，i = 1，2；每个符号包含64个像IEEE802.11a的样品）。在MIMO-OFDM模式，长正交频分复用(OFDM)符号，（Ti，i = 1，2），该符号在信号之后传输，提供信道测量能力。短的辅助符号是用于信号检测，自动增益控制，多样性，粗采样和频率同步。为了确保接收到的信号增益控制及时和提供稳定增益的可靠传输，接收器设计人员可以使用短报头来调整接收到的信号强度达到到最佳水平，该调整通过在接收信号路径上可动态调节的各种信号处理元件来实现。
图1 传统的OFDM数据包结构模型
图2 MIMO-OFDM数据包结构模型
长辅助符号被设计用来信道预测和精细频移校正。该信号包括奇偶校验，长度和速率等。有一个短的保护区间（GI）和一个长的保护区间（GI2）组成32或64个数据样本，分别用来作为传统OFDM的长辅助符号和长MIMOQAM和R= 3 /4 条件下的仿真结果。大增益更新循环可以很快的将接收信号调整到期望的范围。小增益更新循环慢慢抚平接收信号，以避免AD转换器达到饱和并且加输入信号电平的收敛快速度。
数字放大器输入信号电平与时间关系
数字放大器输出信号电平与时间关系
图10 数字放大器输入/输出信号电平
8、结论
在本论文中，设计的自动增益控制电路用来调整接收信号的强度，通过接收路径上可以处理各种信号的大动态范围元件来使接收信号达到一个恒定的最佳能量水平附近。该自动增益控制电路包括一个大增益更新循环和一个小增益更新循环，用来加快收敛速度，并且同时保持自动增益控制电路的稳定。此外，它可以用来动态控制由多径衰落、时间和频率偏移引起大变化范围接收信号的增益，以确保及时地对接收信号进行增益控制，提供稳定增益进而得到可靠的传输。
参考文献
[1] Heejung Yu et al., IEEE 802.11 wirele LANs ETRI proposal specification for IEEE 802.11 TGn, IEEE 802.11 document, doc.No.1104092300000n, August, 2004.[2] H.Yu, T.Jeon, S.Lee, Design of dualband MIMO-OFDM system for next generation wirele LAN, in: IEEE International Conference on Communications(ICC), May, 2005.[3] V.P.G.Jimenez, M.J.F.G.Garcia, F.J.G.Serrano, A.G.Armada, Design and implementation of synchronization and AGC for OFDMbased WLAN receivers, IEEE Trans.Consum.Electron.50(4)(2004)1016–1025.[4] A.Fort, W.Eberle, Synchronization and AGC proposal forIEEE 802.11a burst OFDM systems, GLOBECOM 3(12)(2003)1335–1338.Efficient automatic gain control algorithm and architecture for
wirele LAN receivers
IlGu Lee *, SokKyu Lee Next Generation Wirele LAN Research Team, ETRI, 161 Gajeongdong, Yuseonggu, Daejeon 305700, Republic
of Korea Received 23 February 2006;received in revised form 31 October 2006;accepted 1 November 2006
Available online 11 January 2007 Abstract The performance of a receiver frontend limits the quality and range of the given communication link.An appropriate design based on welldefined system parameters and architecture can make a huge difference in the performance, cost and marketability of the entire system.In particular, there is a need for improved digital automatic gain control(AGC)for use in multiinput multioutput orthogonal frequency division multiplexing(MIMOOFDM)systems with application to wirele local area networks(WLANs), targeted for the upcoming 802.11n standard [Heejung Yu et al., IEEE 802.11 wirele LANs ETRI proposal specification for IEEE 802.11 TGn, IEEE 802.11 document, doc.No.1104092300000n, August, 2004;H.Yu, T.Jeon, S.Lee, Design of dualband MIMOOFDM system for next generation wirele LAN, in: IEEE International Conference on Communications(ICC), May, 2005].In this paper, we propose an efficient algorithm and implementation of the digital AGC for next generation WLANs.The proposed AGC algorithm has two feedback loops for gain control to improve convergence speed, and at the same time maintains the stability of the AGC circuit.Also, a complete set of parameters for practical implementation is obtained by various experiments with fixed point constraints and accuracy requirements.Keywords: AGC;WLAN;MIMOOFDM;Receiver architecture
1.Introduction AGC circuits are employed in many systems where the level of an incoming signal can vary over a wide dynamic range.In high data rate digital communication systems, and especially in burst packet switched systems such as WLANs, the start of each packet introduces a large signal variation.To demodulate a received signal with an improved signaltonoise ratio, AGC can be used to hold the average power of the baseband signal close to a desired level.AGC implementation of highthroughput MIMOOFDM applications to nextgeneration WLANs is important to ensuring achievable operating SNR at the receiver and, consequently, achievable data rates.There have been several research contributions that provide automatic gain control algorithms and present implementation iues.In [3,4], the authors present the implementation of a simple digital automatic gain control architecture targeting the IEEE 802.11a standard.The authors of [3] propose a simple multistop AGC scheme.In [4],an AGC interface with a synchronization scheme based on double autocorrelation is proposed.In those papers, the theoretical problem is analyzed and simulation results are provided without considering implementation constraints in detail.In this paper, the proposed architecture includes a large gain update loop and a small gain update loop to improve convergence speed and at the same time maintain the stability of the AGC circuit.Moreover, it can be used to dynamically control the gain of the received signal for MIMOOFDM systems with large variations in received signal power caused by multipath fading with time and frequency offset.The remainder of this paper is organized as follows.In Section 2, the frame model is given for next generation wirele LANs, and the overall receiver architecture is presented in Section 3.A detailed description for each subblock is then provided in their respective sections: automatic gain control in Section 4;carrier sensing block in Section 5;and digital amplifier in Section 6.In Section 7, the performance of the proposed design is shown.Finally, we conclude in Section 8.2.Frame model The next generation WLAN is a packetbased highthroughput MIMOOFDM system in the 5 GHz band.Figs.1 and 2 show the packet structure of next generation WLAN as specified by [1,2].Each packet contains a header for detection, channel estimation and synchronization.This preamble is known at both sides of the communication link.The legacy OFDM packet preamble consists of 10 identical short OFDM training symbols ti, i =1,2,...,10, each of which contains 16 samples;and two identical long OFDM symbols Ti, i =1,2, each of which contains 64 samples as in the IEEE 802.11a.For MIMOOFDM mode, two long OFDM symbols Ti, i = 3,4, are transmitted after the signal field for providing channel measurement capability.The short training symbols are intended for signal detection, automatic gain control, diversity, coarse acquisition, and frequency synchronization purposes.In order to ensure timely gain control for the received signal and provide reliable transmiion with stable gain, a receiver designer can use the short preamble to adjust the strength of the received signal to an optimum level within the dynamic range of various signal proceing components in the received signal path.Fig.1.The packet structure of the Legacy OFDM mode.Fig.2.The packet structure of the MIMO-OFDM mode.The long training symbols are designed to be used for channel estimation and fine frequency offset correction.The signal field includes information for parity, length and rate, etc.There is a short guard interval(GI)and a long guard interval(GI2)that consist of 32 or 64 data samples for the long legacyOFDM training symbol and the long MIMOOFDM training symbol, respectively.In the OFDM data field, four subcarriers are inserted as pilots into positions 21, 7, 7, and 21 for each band.The total number of subcarriers is 52 and 104 in single and dual band mode, respectively.3.Receiver architecture The overall receiver block diagram is shown in Fig.3.The three received signals from 3 antennas are fed into digital amplifiers to adjust the power of the incoming signals to the target value.The digital front end operations are applied to only the two received signals out of the 3 available paths to reduce implementation complexity.The power of the input signal is measured and gain update is calculated in the AGC block.The digital amplifier output is monitored to detect if the signal is large or not for the carrier sensing purpose.The DC offset and I/Q imbalance that come from RF components and ADC are compensated in each signal path.The received signals are directed to a channel mixer for +10 and 10 MHz frequency shifting.The input OFDM symbol is buffered into the FFT input buffer, and the carrier frequency offset(CFO)is corrected at the input of the FFT.The frequency and phase errors are estimated and corrected by using the pilot tones in the phase tracking block.The CFO estimation, frame synchronization and band detection are performed by an autocorrelation result of short and long preambles.After the synchronization proce is done, the CFO compensated packets are transformed to the frequency domain by a 128point radix23 DIF FFT block.The output of FFT is the data in the bitreversed order, which is fed into the MIMO detector [2], which uses the zeroforcing(ZF)method.Fig.3.The front-end architecture of dual-band MIMO-OFDM receiver with 3 antennas.4.Automatic gain control The amplitude of the received signal is adjusted so that the dynamic range of the ADC can be fully utilized.The state transition diagram implemented physically for the AGC is shown in Fig.4.The AGC block state is changed to the idle state from whatever state the AGC is in when the AGC block enable(agc_en)is deactivated.The first state is a power measurement state(MSR), which determines whether the peak signal is within the dynamic range of ADC before adjusting the amplifier gain.As shown in Fig.5, the signal power is measured by accumulating the absolute real(inphase)and imaginary(quadraturephase)components of each antenna.The power of the input signal is measured for 0.8 ls(32 samples at 40 MHz sampling).Out of the two estimated signal powers, the larger one is selected for gain update.The chosen signal power is converted to a logscale value.It is poible to reduce the range of values by taking log scale for the signal power.If the measured power is out of the dynamic range of ADC(ADC saturation)during this power measurement period, the power measurement is stopped and AGC makes a coarse adjustment with the large gain update state(Update_L)to speed up gain adjustment with the large gain control value.The amplifier gain is reduced right away by the amount of the register programmed value(agc_gainl)in order to speed up convergence.The gain step is fixed to 3 dB.The gain update due to ADC saturation is conducted only when ADC saturation is observed during the signal power measurement period.If ADC is not saturated during the power measurement period, the measured power is compared to a reference power to calculate an error signal, and the magnitude of the error signal is compared to a reference value in a small gain update state(Update_S).By comparing the measured logscale power with the target power that can be selected to maximize the signal to noise ratio and minimize saturation effects.If the measured power(agc_pwr_log)is smaller than the target power(agc_vref), which is a programmable register, then the gain is adjusted so that the signal power is equal to the target power given by the register value after the signal is settled down for the gain change.If the measured signal power is larger than the target power, then the gain is reduced even more given the agc_gains, which is register programmable.This additional gain suppreion will speed up the gain adjustment and prevent saturation when the received signal is large.Once the amplifier gain is updated, the AGC block waits for a register programmed time period(agc_delay)in wait state.This register value should be sufficiently large so that the signal is well settled down to the gain change.The Wait_cont and Wait_last state are the wait states of the continued gain control proce and the last gain control, respectively.Afterthe waiting period, the signal power measurement and gain update is repeated until themeasured power is smaller than the target power and gain is updated accordingly.The initial gain is given by the programmable register(agc_ginit).Fig.4.State digram of AGC block.Fig.5.Block diagram of AGC.5.Digital amplifier
The digital amplifier is used to scale the incoming signal power either by amplifying or attenuating and adjusts it to the target power specified in a programmable register according to the current gain state.The digital amplifier includes a gain state unit that stores the selected gain state for proceing of a received packet.The gain state unit begins with the highest gain state to ensure the lowest power signals can be detected and proceed.The same amount of gain adjustment is applied to the two received signal paths.The implementation of the digital amplifier is simplified by utilizing this coarse gain step as shown in Fig.6.The amount of gain update is divided into 6 dB and 3 dB steps.The 6 dB step gain update is firstly applied to the incoming signal and then the 3 dB step gain adjustment is conducted.When the gain control value is the same as the AGC referencevalue, there is no gain adjustment.Fig.6.Block diagram of digital amplifier.6.Carrier sense by monitoring ADC saturation The existence of the incoming signal is detectedby monitoring whether the ADC is saturated or not.To improve the reliability of detecting the ADC saturation, 16 consecutive samples at 40 MHz sampling are used.Consider one signal component that is a real component from antenna 0.If the number of ADC output sample whose absolute value is larger than a certain threshold(cs_th_sat, 500)is larger than or equal to a register programmable value(cs_th_cnt_sat, 4), then we flag that the ADC is saturated.Any one of the 4 signalcomponents(real and imaginary components from the two antennas)can flag the ADC saturation.A block diagram is shown in Fig.7.Fig.7.Block diagram of carrier sensing.7.Performance evaluation We apply a 50 ns RMS delay spread channel model.As well, RF impairments, a RAPP power amplifier with 10 dB backoff and phase noise with a polezero model, are included.There can be a residual frequency error caused by frequency instabilities in the oscillators at the transmitter andreceiver.All simulation cases have time/frequency offset, introduced by an analogtodigital converter(ADC).Packet size is fixed to 1 K bytes.Simulation modes are fixed to 36 Mbps and 54 Mbps, employing the QPSK, 16QAM and 64QAM modulation schemes, which all employ the dual band with MIMO technique.Therefore, the actual data rate is 72 Mbps, 144 Mbps and 216 Mbps, respectively.The simulated PER using different modulation schemes is plotted in Fig.8.FL and FX refer to the simulated result of floating point version and fixed point version, respectively.Although most modulation schemes of fixed point have similar per formance with floating point, a performance gap due to quantization error is apparent when a 16QAM and 64QAM modulation scheme is utilized, resulting in 0.3 and 0.7 dB SNR lo at PER 10%,respectively.We show that the proposed algorithms and their implementation are effective for multipath fading channel with a 50ns rms delay spreadand 40 ppm time/frequency offset in Fig.8.As well as the known constraint, it requires about 10% PER at 28 dB SNR.Considering the tradeoff between the implementation complexity and the performance, our proposed algorithms and their implementation stand as a good compromised solution for MIMOOFDM receivers.Fig.8.Modulation schemes vs.PER.In Fig.9, the target signal amplitude is adjusted through simulation under 16QAM and R = 3/4.The agc_vref is the target signal amplitude afterAGC is done in terms of the 3 dB step.For example, agc_vref = 13 corresponds to the target signal amplitude of 2^(13/2).We found that the receiver performance is improved by using different settings for signal band use and dual band use, as shown in Table 1.As shown in Table 2, the agc_gainl and agc_gains register values are set considering the PER result, and the range of the input signal power and the number of updates since the AGC should be finished well before the end of the short preamble.The agc_init is the initial gain setting.If the signal needs to be amplified, the gain will be increased up to the maximum.If the signal is large and needs to be suppreed, the gain will be reduced up to 0.When the agc_ginit is 20, the maximum sig nal suppreion will be 20*3 = 60 dB for 3 dB gain control and the maximum signal amplification is(32–20)*3 = 36 dB.The initial gain should be set high enough to suppre the signal.In this example of agc_ginit = 20, there is 60 dB room to suppre the signal.Simulation parameters for the AGC register setting are shown in Table 1.Fig.9.AGC reference value(agc_vref)adjustment.Table 1 Programmable register setting AGC registers agc_delay agc_gainl agc_gains agc_ginit agc_vref
Values 32 12 8 20(dual band use)/10(single band use)
Table 2 AGC loop counts agc_gainl agc_gains # of update_L # of update_S PER(%)0 1 1 6 12 18
Faster convergence of a receiver’s AGC circuit reduces the time required to bring a received signal within the operating range of ADC.The proposed digital AGC circuit includes a large gain update loop and a small gain update loop to improve con vergence speed and maintain stability of the controlled input signal level at the same time, as shown in Fig.10 and simulated at 27 dB with 1000 packets, 64QAM and R = 3/4.The large gain update loop quickly brings the received signal to the desired range.The small gain update loop gradually smoothes the received signal to avoid saturation on the AD converter and speedsup convergence of the input signal level.0 1 4 8 121 4 4 8 4
209 728 648 608 589 721
18.4 16.1 13.3 12.7 12.7 24.6
Fig.10.Input/output signal level of digital amplifier.8.Conclusions In this paper, the proposed AGC circuit is designed to adjust the strength of the received signal to a near constant optimum power level within the dynamic range of various signal proceingcomponents in the received signal path.It includes a large gain update loop and a small gain update loop to improve convergence speed and at the same time maintain the stability of the AGC circuit.Moreover, it can be used to dynamically control the gain of the received signal with large variations caused by multipath fading with time and frequency offset in order to ensure timely gain control for the received signal and provide reliable transmiion with stable gain.References [1] Heejung Yu et al., IEEE 802.11 wirele LANs ETRI proposal specification for IEEE 802.11 TGn, IEEE 802.11 document, doc.No.1104092300000n, August, 2004.[2] H.Yu, T.Jeon, S.Lee, Design of dualband MIMOOFDM system for next generation wirele LAN, in: IEEE International Conference on Communications(ICC), May, 2005.[3] V.P.G.Jimenez, M.J.F.G.Garcia, F.J.G.Serrano, A.G.Armada, Design and implementation of synchronization and AGC for OFDMbased WLAN receivers, IEEE Trans.Consum.Electron.50(4)(2004)1016–1025.[4] A.Fort, W.Eberle, Synchronization and AGC proposal forIEEE 802.11a burst OFDM systems, GLOBECOM 3(12)(2003)1335–1338.
